Edinburgh: Researchers develop ultra-fast Monte-Carlo based financial computing engine

14 Jan 2011 | News

The uncertainty involved in financial modelling means that mathematical techniques such as Monte-Carlo simulation are an important tool for financial applications (eg. bond pricing, risk analysis and market prediction), and can be used to simulate various sources of uncertainty that affect the value of the instrument, portfolio or investment under consideration.

Researchers in the University of Edinburgh's School of Engineering have developed a configuration description for a financial computing engine that delivers the capability to process complex financial models in a fraction of the time required by existing software approaches.

When implemented on reconfigurable hardware (Field Programmable Gate Array - FPGA), this Monte-Carlo based simulation engine for option pricing offers significant performance enhancement with added advantages of re-programmability. The speed up is due to the exploitation of high levels of process parallelisation and careful FPGA block design and mapping.

Key Benefits

  • High performance data processing for financial models – 340x faster than equivalent software implementation
  • Computation of Monte-Carlo based simulation in less than a minute that would require several hours on a workstation
  • Low power consumption and hardware footprint
  • Reconfigurable platform – eliminating non-recurring engineering costs of other hardware solutions
  • Versatile integration – configuration is captured in platform independent Verilog language

Applications

  • Mathematical simulation for financial computing:
  • GARCH Financial Option Pricing (European, American and Asian)
  • Log-normal price movement
  • Correlated asset Value-at-Risk calculations

IP Status

An FPGA hardware implementation of the Monte-Carlo simulation core for the GARCH pricing model of European options has been demonstrated to result in 340x speed up compared to equivalent software implementations. This speed-up is scalable to a multi-FPGA solution and is independent of the number of nodes used.

The University of Edinburgh is seeking interest from commercial organisations to in-license this IP core on a non-exclusive basis.

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